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پاورپوینت درباره Architectural Analysis of a DSP Device, the Instruction Set and the Addressing Modes

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پاورپوینت درباره Architectural Analysis of a DSP Device, the Instruction Set and the Addressing Modes


پاورپوینت درباره Architectural Analysis of a DSP Device, the Instruction Set and the Addressing Modes

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Outline

FIR filter on ADPS-21x

 

DSP Requirements

Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
 Dual Operand Fetch (Memory)
 Circular Buffering (Addressing)
 Zero-Overhead Looping (Instruction set)
 

Analog Devices Architectures and Programming

SHARC
Blackfin
Performance Optimization
 
 
FIR filter steps
Obtain a sample with the ADC; generate an interrupt
Detect and manage the interrupt
Move the sample into the input signal's circular buffer
Update the pointer for the input signal's circular buffer
Zero the accumulator
Control the loop through each of the coefficients
Fetch the coefficient from the coefficient's circular buffer
Update the pointer for the coefficient's circular buffer
Fetch the sample from the input signal's circular buffer
Update the pointer for the input signal's circular buffer
Multiply the coefficient by the sample
Add the product to the accumulator
Move the output sample (accumulator) to a holding buffer
Move the output sample from the holding buffer to the DAC
 

 


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پاورپوینت درباره Architectural Analysis of a DSP Device, the Instruction Set and the Addressing Modes